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There must be "takenism" in the schematic design. Now the chip manufacturers can generally provide the schematic diagram of the reference design, so try to use these resources as much as possible to make some of your own play on the basis of fully understanding the reference design. When the main chip is selected, the key peripheral design includes the power, clock and inter-chip interconnects.

The power supply is the basis for ensuring the normal operation of the hardware system. The design should be analyzed in detail: the power input that the system can provide; the power output that the board needs to generate; the current that each power supply needs to provide; the power circuit efficiency; the allowable fluctuation of each power supply. Range; power-up sequence required for the entire power system, and so on.

For example, the network processor in the A project requires 1.25V as the core voltage, the required accuracy is between +5% and -3%, and the current needs about 12A. According to these requirements, the design uses 5V power input, and uses the linear switching power supply. The controller and the IR MOSFET set up a suitable power supply circuit. The accuracy requirement determines the ESR selection of the output capacitor, and the remote feedback function is added to prevent the voltage drop caused by excessive current.

The realization of the clock circuit should take into account the jitter of the target circuit. The GE PHY device is used in the A project. At the beginning, a zero-delay clock distribution chip with a phase-locked loop is used to provide a 100MHz clock. The result is a GE link. A packet loss occurred on it, and later replaced with a simple clock Buffer device to solve the packet loss problem. The analysis shows that the internal phase-locked loop introduces jitter.

The interconnection between the chips is to ensure the error-free transmission of data. In this respect, the high-speed differential signal lines have the characteristics of high speed, good wiring, good signal integrity, etc. The multi-chip interconnections in the A project use high-speed differential. Signal line, no problems in debugging and testing.