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Machineware----RISC-V

1. Company background

Founded in 2022 in Aachen, Germany, MachineWare leverages decades of experience in system level simulation and high-performance simulation tooling.

2. Product introduction

2.1 RISC-V PRODUCTS

RISC-V is a customizable, open-standard Instruction Set Architecture without license cost or legacy baggage, but with the flexibility to realize your ideas. Today’s most-used software stacks, such as Linux, Android and Chrome, already run on RISC-V and more are to follow - from Embedded to HPC. MachineWare is built on decades of experience in ultra-fast, interoperable simulation technology.  Leverage our solutions to jumpstart your RISC-V project and begin development now.

2.1.1 SIM-V?

SIM-V? is our ultra-fast, functional RISC-V instruction set simulator. It enables you to verify your RISC-V software before hardware becomes available. Its rapid simulation speed reduces test runtimes, enabling your teams to reap detailed results sooner. All the while reducing energy consumption and saving time and money.

Simulating just the CPU might not be sufficient to cover all your use cases.  Simulate your entire SoC by integrating SIM-V? into a full-system simulator or Virtual Platform (VP).  We offer starting point VPs for high-performance and embedded target applications based on our

open-source modeling library VCML. By using VCML you can integrate our models into any SystemC-compatible simulation environment.

MachineWare offers customized versions of SIM-V for different use cases:

(1) SIM-V Compute design and validation for high-performance RISC-V systems, including hardware models for Gpus and high-speed PCIes interconnects.

(2) The SIM-V Edge is optimized for the compact design of 32-bit edge computing systems, providing a wide range of I/O from the microcontroller design space.

Both simulators are built on MachineWare's open source SystemC modeling library, VCML, and can be easily integrated into existing validation Settings and SystemC platform models while providing tracking, analysis, and scripting capabilities.

SIM-V is also based on MachineWare's fast and flexible instruction set simulation framework FTL. This makes it easy to customize the emulator to add custom RISC-V instruction set extensions, and even to design a fully customized instruction set emulator for almost any microprocessor architecture.

2.1.2 SIM-V? Extension SDK

Customizability is at the h(e)art of RISC-V. With our intuitive SIM-V? extension SDK you can quickly add custom instructions and registers to SIM-V?. Simply plug your extension into our RISC-V reference model and get immediate feedback on your design choices.

2.2 ARMPRODUCTS

ARM remains the predominant choice for embedded architecture. Take advantage of our high-speed ARM simulation models, to expedite the launch of your ARM-based product.

2.2.1 SIM-A?

SIM-A?, our cutting-edge, high-speed ARM instruction set simulator, is specifically designed to target ARM Cortex-M and Cortex-A architectures. Leveraging the groundbreaking FTL technology of MachineWare, it empowers you to thoroughly validate your ARM software even before the hardware is accessible. With its exceptional simulation speed, SIM-A? significantly shortens test durations, allowing your teams to access comprehensive results more quickly. This not only conserves energy but also leads to substantial time and cost savings.

2.2.2 ARM-on-ARM

When chips are available, executing target software natively (ARM-on-ARM) outclasses any instruction set simulator. Our solution combines native execution with the rich introspection and analysis capabilities of a Virtual Platform (VP) at rocket speed. Thanks to SystemC’s interoperability, you can seamlessly switch between silicon and simulator at any point.

2.3 SIMULATION PRODUCTS

Besides ultra-fast instruction set simulators for RISC-V, ARM and custom processor architectures, MachineWare offers even more exciting simulation products that accelerate your design.

2.3.1 Fast Processor Models

MachineWare processor models are based on our processor modeling toolkit FTL, which leverages Just-In-Time compilation techniques to maximize simulation performance. FTL is suitable for modeling many processor architectures - even weird ones, like ARM.

2.3.2 Hardware-Accelerated Simulation

Relying solely on software simulation has its limits, as there will always be some inherent overhead.  Achieving a significant boost in simulation speed necessitates the utilization of hardware acceleration by the simulation host. MachineWare provides various solutions for incorporating host hardware into the simulation process, thereby optimizing performance, all while maintaining compatibility with the SystemC TLM-2.0 standard.

2.3.3 InSCight?

InSCight? is MachineWare's solution for profiling Virtual Platforms (VPs).  It consists of two parts: The MachineWare SystemC simulation kernel that logs simulation data into a database during simulation runtime, and a desktop application that can load this simulation database and visualize the simulation data.  The product is used to profile simulations of Virtual Platforms, i.e., to analyze them dynamically.  This makes it easy to find and fix logical errors and bottlenecks in the simulation, thus improving the quality of the simulation results and the simulation performance.

2.3.4 QBox

QEMU is a popular open-source simulator with a large library of processor and peripheral models.  However, it is limited in flexibility as it offers no standardized interfaces.  QBox (Qemu in SystemC Box) extends QEMU with SystemC TLM-2.0 interfaces, enabling the usage of QEMU processor and peripheral models in any SystemC TLM-2.0 simulation.

3.0 Conclusion

MachineWare's Virtual Prototypes simulate your hardware at bit-level accuracy, shortening development time and enhancing software security, stability, and quality. Support for ARM, RISC-V and custom processor architectures.

Check out our open-source SystemC TLM-2.0 productivity library VCML. It comes with many free component models for standard components such as UARTs, NICs and more. All model building blocks and interfaces are part of the open-source releas